The present application claims priority to Japanese Application(s) No(s) P2001-041790 filed Feb. 19, 2001, which application(s) is/are incorporated herein by reference to the extent permitted by law.
The present invention relates to a semiconductor device and a process for fabrication thereof. More particularly, the present invention relates to a semiconductor device having a capacitive element of MIMC structure and a process for fabrication thereof.
There are two types of conventional capacitive elements formed on the semiconductor substrate (such as silicon substrate). One is of MIS capacitor structure which is characterized in that a low-resistance diffused layer formed in the semiconductor substrate functions as the lower electrode layer. Another is of MIMC structure which is characterized in that a conductive layer formed on an insulating film on the semiconductor substrate functions as the lower electrode layer. Conventional capacitive elements of MIS capacitor structure and MIMC structure are briefly explained in the following with reference to FIG. 11 and FIG. 12, respectively.
A conventional capacitive element of MIS capacitor structure is shown in FIG. 11. It has a p-type semiconductor substrate 60, a field oxide film 62 on the surface of the substrate, and an element region isolated by a p+-type element isolating region 64 under the field oxide film. In the element region is an n-type impurity diffused layer 66 which functions as the lower electrode. On the n-type impurity diffused layer 66 (which functions as the lower electrode) is formed a first upper wiring layer 70a (which functions as the upper electrode), with a SiN dielectric layer 68 interposed between them. A second upper wiring layer 70b is formed which is connected to the n-type impurity diffused layer 66 (which functions as the lower electrode) through a via hole made in an interlayer insulating film 72 and the SiN dielectric layer 68. Thus, the capacitive element 74 of MIS capacitor structure is constructed such that the SiN dielectric layer 68 is held between the n-type impurity diffused layer 66 (which functions as the lower electrode) and the first upper wiring layer 70a (which functions as the upper electrode). There exists a parasitic capacity between the capacitive element 74 of MIS capacitor structure and the p-type semiconductor substrate 60. This parasitic capacity is dominated by the PN junction capacity between the n-type impurity diffused layer 66 (which functions as the lower electrode) and the p-type semiconductor substrate 60.
A conventional capacitive element of MIMC structure is shown in FIG. 12. It has a p-type semiconductor substrate 60 and a lower wiring layer 78 (which functions as the lower electrode), with an insulating film 76 interposed between them. On the lower wiring layer 78 (which functions as the lower electrode) is formed a first upper wiring layer 82a, with a SiN dielectric layer 80 interposed between them. A second upper wiring layer 82b is formed which is connected to the lower wiring layer 78 (which functions as the lower electrode) through a via hole made in an interlayer insulating film 84.
Thus, the capacitive element 86 of MIMC structure is constructed such that the SiN dielectric layer 80 is held between the lower wiring layer 78 (which functions as the lower electrode) and the first upper wiring layer 82a (which functions as the upper electrode). There exists a parasitic capacity between the capacitive element 86 of MIMC structure and the p-type semiconductor substrate 60. This parasitic capacity is dominated by the capacity between the lower wiring layer 78 (which functions as the lower electrode) and the p-type semiconductor substrate 60.
On account of their construction mentioned above, there is a difference in parasitic capacity between the conventional capacitive element 74 of MIS capacitor structure and the conventional capacitive element 86 of MIMC structure. Usually, the latter permits its parasitic capacity to be reduced more easily than the former, because the insulating film 76 is thick. In addition, the latter is particularly suitable for high-frequency applications. Therefore, the capacitive element of MIMC structure is usually employed if it is necessary for the capacitive element to have a high capacity, a low parasitic capacity, and a low parasitic resistance.
Although the conventional capacitive element of MIMC structure has a smaller parasitic capacity as compared with that of MIS capacitor structure, it cannot be freed of its parasitic capacity completely because there exists a semiconductor substrate under the capacitive element, with an insulating film interposed between them. In order to realize a high-performance capacitive element with a low parasitic capacity, it is necessary to reduce further the parasitic capacity of the capacitive element of MIMC structure.
One way to meet this requirement is to employ an SOI (Silicon On Insulator) substrate having an insulating film. The use of this substrate greatly helps to reduce parasitic capacity. Unfortunately, this substrate suffers the disadvantage of complicating the steps for fabrication of integrated circuits, which is economically unjustifiable.
There is another way of reducing parasitic capacity by making thicker the interlayer insulating film between the semiconductor substrate and the capacitive element of MIMC structure. The disadvantage of this way is a necessity to form a deeply stepped electrode for connection of wires in multi-layer structure. Connection in this manner tends to cause incomplete contact.
The present invention was completed in view of the foregoing. It is an object of the present invention to provide a semiconductor device in which the capacitive element of MIMC structure has a reduced parasitic capacity. It is another object of the present invention to provide a process for fabrication of the semiconductor device.
The above-mentioned objects are achieved by the semiconductor device and the process for fabrication thereof as set forth in the appended claims.
The first aspect of the present invention is directed to a semiconductor device which has a capacitive element on an insulating film formed on a semiconductor substrate, the capacitive element including a lower electrode layer, a dielectric layer, and an upper electrode layer, wherein a semiconductor layer of prescribed conductivity type having a lower impurity concentration than the semiconductor substrate, is formed between the semiconductor substrate and the insulating film.
The semiconductor device defined in the first aspect of the present invention includes the capacitive element of MIMC structure (or the capacitive element in which a lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially laminated on an insulating film) has a semiconductor layer of prescribed conductivity type with a lower impurity concentration than the semiconductor substrate which is interposed between the lower insulating film and the semiconductor substrate. This construction reduces the parasitic capacity of the capacitive element of MIMC structure.
In addition, this construction makes it unnecessary to use an SOI substrate which complicates fabrication of integrated circuits and to use a high-resistance semiconductor substrate which is difficult to produce. This avoids cost increase and latch-up due to parasitic elements. This construction does not need an unduly thick insulating film which is interposed between the semiconductor substrate and the capacitive element of MIMC structure. This avoids defective contact of wiring between layers of multi-layer wiring structure.
The second aspect of the present invention is directed to a semiconductor device in which a capacitive element and a photodiode are mounted together on the same semiconductor substrate. This semiconductor device includes: a semiconductor layer of prescribed conductivity type with a lower impurity concentration than the semiconductor substrate is formed on the semiconductor substrate; a low-concentration semiconductor layer of the semiconductor layer of prescribed conductivity type and a semiconductor layer which becomes either an anode or cathode are formed respectively in the capacitive element forming region and the photodiode forming region; and a capacitive element consisting of a lower electrode layer, a dielectric layer, and an upper electrode layer which are sequentially laminated on the low-concentration semiconductor substrate, with an insulating film interposed between them, wherein a semiconductor layer which becomes an anode or cathode of semiconductor layer having a conductivity type opposite to the semiconductor layer of prescribed conductivity type is formed on the semiconductor layer which becomes either an anode or a cathode.
xe2x80x9cThe semiconductor layer which becomes either an anode or a cathode of photodiodexe2x80x9d means the semiconductor layer which becomes the cathode of the photodiode when the semiconductor layer which becomes, for instance, the anode of the photodiode by the semiconductor layer of prescribed conductivity type, or the semiconductor layer which becomes the anode of the photodiode when the semiconductor layer which becomes, for instance, the cathode of the photodiode by the semiconductor layer of prescribed conductivity type. This definition is applied hereinafter.
The semiconductor device pertaining to the second aspect of the present invention, in which a capacitive element and a photodiode are mounted together on the same substrate includes a semiconductor layer with a lower impurity concentration than the semiconductor substrate is formed on the substrate in the capacitive element region, and a capacitive element consisting of a lower electrode layer, a dielectric layer, and an upper electrode layer which are sequentially laminated is formed on the low-concentration semiconductor layer, with an insulating film interposed between them. In other words, the capacitive element of MIMC structure is constructed such that a low-concentration semiconductor layer is interposed between the semiconductor substrate and the lower insulating film. This construction suppresses the parasitic capacity of the capacitive element of MIMC structure.
The semiconductor device is constructed such that the low-concentration semiconductor layer under the capacitive element of MIMC structure and the semiconductor layer which becomes either the anode or cathode of the photodiode is the semiconductor layer of prescribed conductivity type formed on the semiconductor substrate. This construction permits the steps to be carried out in common for fabrication of the semiconductor device in which the capacitive element and the photodiode are mounted together on the same semiconductor substrate. This leads to cost reduction.
The third aspect of the present invention is directed to a semiconductor device in which a capacitive element, a photodiode, and a bipolar transistor are mounted all together on the same semiconductor substrate, the semiconductor device includes a semiconductor layer of prescribed conductivity type having a lower impurity concentration than the substrate is formed on the substrate; a low-concentration semiconductor layer of this semiconductor layer of prescribed conductivity type, a semiconductor layer which becomes either an anode or cathode, and a semiconductor layer for substrate are formed in the photodiode forming region and the bipolar transistor forming region; a capacitive element consisting of a lower electrode layer, a dielectric layer, and an upper electrode layer sequentially laminated is formed on the low-concentration semiconductor layer, with an insulating film interposed between them; and a semiconductor layer of prescribed conductivity type and a semiconductor layer of opposite conductivity type are formed on the semiconductor layer which becomes either an anode or cathode; wherein the semiconductor layer for substrate, and a semiconductor layer which becomes the other of either an anode or cathode of the semiconductor layer of opposite conductivity type and a collector layer are formed.
Incidentally, the term xe2x80x9csemiconductor layer substratexe2x80x9d means any semiconductor layer which functions as an ordinary substrate for a bipolar transistor. This definition is applicable throughout the description that follows.
The semiconductor device pertaining to the third aspect of the present invention has a capacitive element, a photodiode, and a bipolar transistor which are mounted all together on the same semiconductor substrate, such that a semiconductor layer having a lower impurity concentration than the substrate is formed on the substrate in the capacitive element forming region, and a capacitive element including a lower electrode layer, a dielectric layer, and an upper electrode layer sequentially laminated is formed on the low-concentration semiconductor layer, with an insulating film interposed between them. In other words, a low-concentration semiconductor layer is interposed between the semiconductor substrate and the insulating film under the capacitive element of MIMC structure. As in the case of the first aspect mentioned above, this construction suppresses the parasitic capacity of the capacitive element of MIMC structure.
In addition, the low-concentration semiconductor layer under the capacitive element of MIMC structure, the semiconductor layer which becomes either the anode or cathode of the phototransistor, and the semiconductor layer for substrate of the bipolar transistor are formed from the semiconductor layer of prescribed conductivity type which is formed on the semiconductor substrate. And the semiconductor layer which becomes either the anode or cathode of the photodiode and the collector layer of the bipolar transistor are formed from the semiconductor layer of opposite conductivity type formed on the semiconductor layer of prescribed conductivity type. This construction permits the steps to be carried out in common for fabrication of the semiconductor device in which the capacitive element, the photodiode, and the bipolar transistor are mounted together on the same semiconductor substrate. This leads to cost reduction.
Preferably, the fourth aspect of the present invention is concerned with the semiconductor device defined in any of the first to third aspects mentioned above, in which the lower electrode layer of the capacitive element is formed from TiN.
Preferably, the fifth aspect of the present invention is concerned with the semiconductor device defined in any of the first to third aspects mentioned above, in which the dielectric layer of the capacitive element is formed from Ta2O5.
Preferably, the sixth aspect of the present invention is concerned with the semiconductor device defined in any of the first to third aspects mentioned above, in which the upper electrode layer of the capacitive element is formed from TiN.
Preferably, the seventh aspect of the present invention is concerned with the semiconductor device defined in any of the first to third aspects mentioned above, in which the impurity concentration of the semiconductor layer of prescribed conductivity type is no lower than 1xc3x971013 cmxe2x88x923 and no higher than 5xc3x971014 cmxe2x88x923.
Preferably, the eighth aspect of the present invention is concerned with the semiconductor device defined in any of the first to third aspects mentioned above, in which the semiconductor layer of prescribed conductivity type has an impurity concentration no lower than 1xc3x971013 cmxe2x88x923 and no higher than 5xc3x971014 cmxe2x88x923 and the semiconductor layer whose conductivity type is opposite to that of the semiconductor layer of prescribed conductivity type has an impurity concentration no lower than 1xc3x971015 cmxe2x88x923 and no higher than 5xc3x971016 cmxe2x88x923.
The ninth aspect of the present invention is directed to a process for fabrication of a semiconductor device, the process includes the steps of: a first step of forming on a semiconductor substrate a semiconductor layer having a lower impurity concentration than the semiconductor substrate; a second step of forming an insulating film on the semiconductor layer; and a third step of forming on the semiconductor layer a capacitive element by sequentially laminating a lower electrode layer, a dielectric layer, and an upper electrode layer.
The process for fabrication of a semiconductor device according to the ninth aspect of the present invention includes the steps of: a first step of forming on a semiconductor substrate a semiconductor layer having a lower impurity concentration than the semiconductor substrate; a second step of forming an insulating film on the semiconductor layer; and a third step of forming on the semiconductor layer a capacitive element by sequentially laminating a lower electrode layer, a dielectric layer, and an upper electrode layer. In other words, when the capacitive element of MIMC structure is formed, a semiconductor layer of prescribed conductivity type having a lower impurity concentration than the semiconductor substrate is formed between the semiconductor substrate and the insulating film thereunder. This construction suppresses the parasitic capacity of the capacitive element of MIMC structure.
The tenth aspect of the present invention is directed to a process for fabrication of a semiconductor device in which a capacitive element and a photodiode are mounted together on the same substrate, the process includes the steps of: a first step of forming on a semiconductor substrate a semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, thereby forming a low-concentration semiconductor layer in the capacitive element forming region and a semiconductor layer which becomes either the anode or cathode in the photodiode forming region; a second step of forming on the semiconductor layer of a first conductivity type a semiconductor layer of a second conductivity type, thereby forming a semiconductor layer which becomes either the anode or cathode in the photodiode forming region; a third step of performing selective oxidation on the semiconductor layer of a second conductivity in the capacitive element forming region, thereby forming an insulating film on the semiconductor layer of a first conductivity type, and a fourth step of forming on the insulating film a capacitive element by sequentially laminating a lower electrode layer, a dielectric layer, and an upper electrode layer.
The process for fabrication of a semiconductor device according to the tenth aspect of the present invention includes a semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate formed on a semiconductor substrate, thereby forming a low-concentration semiconductor layer, forming on the semiconductor layer of a first conductivity type a semiconductor layer of a second conductivity type, forming an insulating layer by selective oxidation, forming on the insulating layer a capacitive element by sequentially laminating a lower electrode layer, a dielectric layer, and an upper electrode layer. In other words, when the capacitive element of MIMC structure is formed, a low-concentration semiconductor layer is formed between the semiconductor substrate and the insulating film thereunder. This construction suppresses the parasitic capacity of the capacitive element of MIMC structure as in the case of the ninth aspect mentioned above.
According to this process, the low-concentration semiconductor layer under the capacitive element of MIMC structure and the semiconductor layer which becomes either the anode or cathode of the photodiode are formed simultaneously by formation of the semiconductor layer of a first conductivity type on the semiconductor substrate. This construction permits the steps to be carried out in common for fabrication of the semiconductor device in which the capacitive element and the photodiode are mounted together on the same semiconductor substrate. This leads to cost reduction.
The eleventh aspect of the present invention is directed to a process for fabrication of a semiconductor device in which a capacitive element, a photodiode, and a bipolar transistor are mounted together on the same substrate, the process includes the steps of: a first step of forming on a semiconductor substrate a semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, thereby forming a low-concentration semiconductor layer in the capacitive element forming region and forming a semiconductor layer which becomes either the anode or cathode in the photodiode; a second step of forming on the semiconductor layer of a first conductivity type a semiconductor layer of a second conductivity type, thereby forming a semiconductor layer which becomes either the anode or cathode in the photodiode forming region and a collector layer in the bipolar transistor forming region; a third step of performing selective oxidation on the semiconductor layer of a second conductivity in the capacitive element forming region, thereby forming an insulating film on the semiconductor layer of a first conductivity type; and a fourth step of forming on the insulating film a capacitive element by sequentially laminating a lower electrode layer, a dielectric layer, and an upper electrode layer.
The process for fabrication of a semiconductor device according to the eleventh aspect of the present invention includes a semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate formed on a semiconductor substrate, thereby forming a low-concentration semiconductor layer, and performing selective oxidation on the semiconductor layer of a second conductivity formed on the semiconductor layer of a first conductivity type, thereby forming an insulating film, and forming on this insulating film a capacitive element by sequentially laminating a lower electrode layer, a dielectric layer, and an upper electrode layer. In other words, when the capacitive element of MIMC structure is formed, a low-concentration semiconductor layer is formed between the semiconductor substrate and the insulating film thereunder. This construction suppresses the parasitic capacity of the capacitive element of MIMC structure as in the case of the ninth aspect mentioned above.
According to this process, the low-concentration semiconductor layer under the capacitive element of MIMC structure, the semiconductor layer which becomes either the anode or cathode of the photodiode, and the semiconductor layer for substrate of the bipolar transistor are formed simultaneously by formation of the semiconductor layer of a first conductivity type on the semiconductor substrate, and the semiconductor layer which becomes either the anode or cathode of the photodiode and the collector layer of the bipolar transistor are formed simultaneously by formation of the semiconductor layer of a second conductivity type on the semiconductor layer of a first conductivity type. This construction permits the steps to be carried out in common for fabrication of the semiconductor device in which the capacitive element, the photodiode, and the bipolar transistor are mounted together on the same semiconductor substrate. This leads to cost reduction.
Preferably, the twelfth aspect of the present invention is concerned with a modification of the process for fabrication of a semiconductor device defined in the tenth or eleventh aspect mentioned above, the modification being characterized in that when the semiconductor layer of a second conductivity type in the capacitive element forming region is selectively oxidized and the insulating film is formed on the semiconductor layer of a first conductivity type, the semiconductor layer of a second conductivity type in the element isolating part is also selectively oxidized at the same time, thereby the field oxide film is formed.
In this case, the insulating film under the capacitive element of MIMC structure and the field oxide film in the element isolating part are formed simultaneously by selective oxidation of the semiconductor layer of a second conductivity type. This construction permits the steps to be carried out in common for fabrication of the semiconductor device in which the capacitive element etc. are mounted together on the same semiconductor substrate. This leads to further cost reduction.
Preferably, the thirteenth aspect of the present invention is concerned with a modification of the process for fabrication of a semiconductor device defined in the eleventh aspect mentioned above, the modification includes an additional step of incorporating an impurity of prescribed conductivity type into the semiconductor layer for substrate after the semiconductor layer of a first conductivity type having a lower impurity concentration lower than the substrate is formed on the semiconductor substrate, thereby a low-concentration semiconductor layer is formed in the capacitive element forming region and the semiconductor layer for substrate is formed in the bipolar transistor forming region.
In this case, it is possible to control the impurity concentration in the semiconductor layer for substrate which functions as the substrate of the bipolar transistor, for matching with the impurity concentration of the substrate required to realize the desired characteristics. In this way the bipolar transistor having the desired characteristics is fabricated.